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MOTOROLA
Order this document by MC68HC812A4EC/D
7/28/98
SEMICONDUCTOR
TECHNICAL DATA
Technical Supplement MC68C812A4 3.3V Electrical Characteristics
The MC68C812A4 is the low-voltage version of the standard MC68HC812A4 microcontroller unit (MCU), a 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include a 16-bit central processing unit (CPU12), a Lite integration module (LIM), two asynchronous serial communications interfaces (SCI0 and SCI1), a serial peripheral interface (SPI), a timer and pulse accumulation module, an 8-bit analog-to-digital converter (ATD), 1-Kbyte RAM, 4-Kbyte EEPROM, and memory expansion logic with chip selects, key wakeup ports, and a phase-locked loop (PLL). This supplement contains the most accurate electrical information for the MC68C812A4 microcontroller available at the time of publication. The information should be considered preliminary and is subject to change. The following characteristics are contained in this document: Table 1 Maximum Ratings Table 2 Thermal Characteristics Table 3 DC Electrical Characteristics Table 4 Supply Current Table 5 ATD Maximum Ratings Table 6 ATD DC Electrical Characteristics Table 7 Analog Converter Characteristics (Operating) Table 8 ATD AC Characteristics (Operating) Table 9 EEPROM Characteristics Table 10 Control Timing Table 11 Peripheral Port Timing Table 12 Non-Multiplexed Expansion Bus Timing Table 13 SPI Timing
PRELIMINARY
(c) MOTOROLA INC, 1997, 1998
Table 1 Maximum Ratings1
Rating Supply voltage Input voltage Operating temperature range MC68C812A4PV5 Storage temperature range Current drain per pin3 Excluding VDD and VSS VDD differential voltage
2
Symbol VDD, VDDA, VDDX VIN TA Tstg IIN VDD-VDDX
Value -0.3 to +6.5 -0.3 to +6.5 TL to TH 0 to +70 -55 to +150 25 6.5
Unit V V C C mA V
PRELIMINARY
NOTES: 1. Permanent damage can occur if maximum ratings are exceeded. Exposures to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Refer to MC68HC812A4TS/D Technical Summary for complete part numbers. 3. One pin at a time, observing maximum power dissipation limits. Internal circuitry protects the inputs against damage caused by high static voltages or electric fields; however, normal precautions are necessary to avoid application of any voltage higher than maximum-rated voltages to this highimpedance circuit. Extended operation at the maximum ratings can adversely affect device reliability. Tying unused inputs to an appropriate logic voltage level (either GND or VDD) enhances reliability of operation.
Table 2 Thermal Characteristics
Characteristic Average junction temperature Ambient temperature Package thermal resistance (junction-to-ambient) 112-pin thin quad flat pack (TQFP) Symbol TJ TA JA Value TA + (PD x JA) User-determined 39 PINT + PI/O or K ------------------------T J + 273C IDD x VDD User-determined PD x (TA + 273C) + JA x PD2 Unit C C C/W
Total power dissipation1
PD
W
Device internal power dissipation I/O pin power A constant3 dissipation2
PINT PI/O K
W W W * C
NOTES: 1. This is an approximate value, neglecting PI/O. 2. For most applications PI/O PINT and can be neglected. 3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium). Use this value of K to solve for PD and TJ iteratively for any value of TA.
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Table 3 DC Electrical Characteristics VDD = 3.3 Vdc 0.3V, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic Input high voltage, all inputs Input low voltage, all inputs Output high voltage All I/O and output pins Normal drive strength IOH = -10.0 A IOH = -0.8 mA Reduced drive strength IOH = -4.0 A IOH = -0.3 mA Output low voltage, All I/O and output pins, normal drive strength IOL = 10.0 A IOL = 1.6 mA VOL EXTAL, PAD[7:0], VRH, VRL, VFP, XIRQ, reduced drive strength IOL = 3.6 A IOL = 0.6 mA Input leakage current1 all inputs except IRQ, PAD7, and XFC Vin = VDD or VSS IRQ, PAD7, XFC Three-state leakage, I/O ports, BKGD, and RESET Input capacitance All input pins and ATD pins (non-sampling) ATD pins (sampling) All I/O pins Output load capacitance All outputs except PS[7:4] PS[7:4] Active pull-up, pull-down current IRQ, XIRQ, ECLK, LSTRB, R/W , BKGD, MODA, MODB, ARST Ports A, B, C, D, F, G, H, J, S, T RAM standby voltage, power down RAM standby current Iin IOZ -- -- -- -- -- -- -- -- -- -- 50 2.0 -- VSS+0.2 VSS+0.4 1 10 2.5 10 15 20 90 130 500 -- 1 V V A A A pF pF pF pF pF A V mA Symbol VIH VIL Min 0.7 x VDD VSS-0.3 Max VDD + 0.3 0.2 x VDD Unit V V
VOH
VDD - 0.2 VDD - 0.8 VDD - 0.2 VDD - 0.8 -- --
-- --
V V
-- -- VSS+0.2 VSS+0.4
V V V V
Cin
CL
IAPU VSB ISB
NOTES: 1. Specification is for parts in the 0 to +70C range. Higher temperature ranges will result in increased current leakage.
MC68C812A4
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PRELIMINARY
Table 4 Supply Current VDD = 3.3 Vdc 0.3V, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic Maximum total supply current RUN: Single-chip mode Expanded mode WAIT: (All peripheral functions shut down) Single-chip mode Expanded mode STOP: Single-chip mode, no clocks Maximum power dissipation1 IDD 15 21 17 25 mA mA Symbol 4 MHz 5 MHz Unit
WIDD
3 3
3.5 3.5
mA mA
SIDD Single-chip mode Expanded mode PD
250 54 76
250 62 90
A mW mW
PRELIMINARY
NOTES: 1. Includes IDD and IDDA.
Note: IDD is tested with a rail-to-rail square wave on EXTAL Table 5 ATD Maximum Ratings
Characteristic ATD reference voltage VRH VDDA VRL VSSA VSS differential voltage VDD differential voltage VREF differential voltage Reference to supply differential voltage Symbol VRH VRL |VSS-VSSA| |VDD-VDDA| VDD-VDDX |VRH-VRL| |VRH-VDDA| |VRL-VSSA| Value -0.3 to +6.5 -0.3 to +6.5 0.1 6.5 6.5 6.5 6.5 6.5 Units V V V V V V V V
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Table 6 ATD DC Electrical Characteristics VDD = 3.3 Vdc 0.3V, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted
Characteristic Analog supply voltage Analog supply current Reference voltage, low Reference voltage, high VREF differential reference voltage1 Input voltage2 Input current, off channel3 Reference supply current Input capacitance Not Sampling Sampling Normal operation Symbol VDDA IDDA VRL VRH VRH-VRL VINDC IOFF IREF CINN CINS VSSA VDDA/2 3.0 VSSA Min 3.0 Max 3.6 1.0 VDDA/2 VDDA 3.6 VDDA 100 250 10 15 Unit V mA V V V V nA A pF pF
NOTES: 1. Accuracy is guaranteed at VRH - VRL = 3.3 Vdc 0.3V. 2. To obtain full-scale, full-range results, VSSA VRL VINDC VRH VDDA. 3. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 10C decrease from maximum temperature.
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PRELIMINARY
Table 7 Analog Converter Characteristics (Operating) VDD = 3.3 Vdc 0.3V, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted
Characteristic 8-bit resolution1 Differential non-linearity2 Integral non-linearity2 Absolute error2,3 2, 4, 8, and 16 ATD sample clocks Symbol 2 counts DNL INL AE RS -0.5 -1 -2 20 Min Typical 24 +0.5 +1 +2 See note4 Max Unit mV count count count K
Maximum source impedance
PRELIMINARY
NOTES: 1. VRH - VRL 3.072V 2. At VREF = 3.072V, one 8-bit count = 12 mV. 3. Eight-bit absolute error of 2 counts (24 mV) includes 1/2 count (6 mV) inherent quantization error and 1 1/2 counts (18 mV) circuit (differential, integral, and offset) error. 4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result value due to junction leakage is expressed in voltage (VERRJ): VERRJ = RS x IOFF where IOFF is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of ATD clock speed, the number of channels being scanned, and source impedance. For 8-bit conversions, charge pump leakage is computed as follows: VERRJ = .25pF x VDDA x RS x ATDCLK/(8 x number of channels)
Table 8 ATD AC Characteristics (Operating) VDD = 3.3 Vdc 0.3V, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted
Characteristic ATD operating clock frequency Conversion time per channel 0.5 MHz fATDCLK 2 MHz 18 ATD clocks 32 ATD clocks Stop recovery time VDDA = 3.3V Symbol fATDCLK Min 0.5 Max 2.0 Unit MHz
tCONV
9.0 16.0
32.0 60.0 50
s s s
tSR
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Table 9 EEPROM Characteristics VDD = 3.3 Vdc 0.3V, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic Minimum programming clock frequency1 Programming time Clock recovery time following STOP, to continue programming Erase time Write/erase endurance Data retention Symbol fPROG tPROG tCRSTOP tERASE 10,000 10 30,000 Min 3.0 20 tPROG+ 1 20 Typical Max Unit MHz ms ms ms cycles years
NOTES: 1. RC oscillator must be enabled if programming is desired and fSYS < fPROG.
Table 10 Control Timing
Characteristic Symbol 5.0 MHz Min Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup time tPCSU = tcyc/2+ 30 fo tcyc fXTAL 2fo tPCSU PWRSTL tMPS tMPH PWIRQ tWRS PWTIM dc 200 -- dc 130 32 2 4 10 420 -- 420 Max 5.0 -- 10.0 10.0 -- -- -- -- -- -- 4 -- MHz ns MHz MHz ns tcyc tcyc tcyc ns ns tcyc ns Unit
Reset input pulse width To guarantee external reset vector Minimum input time (can be preempted by internal reset) Mode programming setup time Mode programming hold time Interrupt pulse width, IRQ, edge-sensitive mode, KWU PWIRQ = 2tcyc + 20 Wait recovery startup time Timer pulse width, input capture pulse accumulator input PWTIM = 2tcyc + 20
MC68C812A4
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PRELIMINARY
PT[7:0]1 PW TIM PT[7:0]2
PT7 1 PW PA PT7 2
NOTES : 1. Rising edge sensitive input 2. Falling edge sensitive input
TIMER INPUT TIMING
Figure 1 Timer Inputs
PRELIMINARY
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MC68C812A4
MC68C812A4
4098 tcyc tPCSU PW RSTL tMPS tMPH FFFE FREE FFFE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC FFFE FFFE FFFE FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC
POR EXT RESET TIM
V DD
EXTAL
ECLK
RESET
MODA, MODB
Figure 2 POR and External Reset Timing Diagram
INTERNAL ADDRESS
NOTE: Reset timing is subject to change.
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PRELIMINARY
PRELIMINARY
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IRQ 1 PW IRQ IRQ or XIRQ tSTOPDELAY 3 ECLK
SP-8 SP-9 FREE FREE SP-6 OPT FETCH 1ST EXEC Resume program with instruction which follows the STOP instruction. SP-6 SP-8 SP-9 FREE VECTOR FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC
INTERNAL CLOCKS
ADDRESS 4
Figure 3 STOP Recovery Timing Diagram
NOTES: 1. Edge Sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0) 3. tSTOPDELAY = 4098 tcyc if DLY bit = 1 or 2 cyc if DLY = 0. t 4. XIRQ with X bit in CCR = 1. 5. IRQ or (XIRQ with X bit in CCR = 0).
ADDRESS 5
STOP RECOVERY TIM
MC68C812A4
MC68C812A4
ECLK tPCSU tWRS ADDRESS
SP - 2 SP - 4 SP - 9 SP - 6 . . . SP - 9 SP - 9 . . . SP - 9 SP - 9 VECTOR ADDRESS FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC
IRQ, XIRQ , OR INTERNAL INTERRUPTS
PC, IY, IX, B:A, , CCR STACK REGISTERS
R/W
Figure 4 WAIT Recovery Timing Diagram
NOTE: RESET also causes recovery from WAIT.
WAIT RECOVERY TIM
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PRELIMINARY
PRELIMINARY
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ECLK tPCSU IRQ 1 PW IRQ IRQ 2, XIRQ , ADDRESS
SP - 2 SP - 4 SP - 6 VECTOR ADDR 1ST PIPE 2ND PIPE SP - 8 SP - 9 3RD PIPE 1ST EXEC
OR INTERNAL INTERRUPT
DATA
VECT
PC
PROG FETCH
IY
IX
PROG FETCH
B:A
CCR
PROG FETCH
Figure 5 Interrupt Timing Diagram
R/W NOTES: 1. Edge sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0)
INTERRUPT TIM
MC68C812A4
Table 11 Peripheral Port Timing
Characteristic Symbol 5.0 MHz Min Frequency of operation (E-clock frequency) E-clock period Peripheral data setup time MCU read of ports Peripheral data hold time MCU read of ports Delay time, peripheral data write MCU write to ports tPDSU = tcyc/2 + 30 fo tcyc tPDSU tPDH tPWD dc 200 130 0 -- Max 5.0 -- -- -- 40 MHz ns ns ns ns Unit
MCU READ OF PORT ECLK
tPDSU PORTS
tPDH
PORT RD TIM
Figure 6 Port Read Timing Diagram
MCU WRITE TO PORT ECLK
tPWD PORT A PREVIOUS PORT DATA NEW DATA VALID
PORT WR TIM
Figure 7 Port Write Timing Diagram
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PRELIMINARY
Table 12 Non-Multiplexed Expansion Bus Timing VDD = 3.3 Vdc 0.3V, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Num Characteristic1 Delay Symbol 5 MHz Min Frequency of operation (E-clock frequency) 1 2 3 5 6 7 11 Cycle time Pulse width, E low Pulse width, E high2 Address delay time Address hold time Address valid time to E rise Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time2 Read/write delay time tDSW = PWEH - tDDW tRWD = tcyc/4 + delay tDDW = tcyc/4 + delay tAV = PWEL - tAD tcyc = 1/fo PWEL = tcyc/2 + delay PWEH = tcyc/2 + delay tAD = tcyc/4 + delay -2 -2 29 -- -- -- -- 25 -- -- 20 -- -- tLSD = tcyc/4 + delay 20 -- -- tACCA = tcyc - tAD - tDSR tACCE = PWEH - tDSR tCSD = tcyc/4 + delay -- -- 29 -- -- tCSN = tcyc/4 + delay 5 fo tcyc PWEL PWEH tAD tAH tAV tDSR tDHR tDDW tDHW tDSW tRWD tRWV tRWH tLSD tLSV tLSH tACCA tACCE tCSD tACCS tCSH tCSN dc 200 98 98 -- 20 28 30 0 -- 20 23 -- 28 20 -- 28 20 -- -- -- -- 0 55 Max 5.0 -- -- -- 79 -- -- -- -- 75 -- -- 70 -- -- 70 -- -- 100 68 79 100 10 -- MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
PRELIMINARY
12 13 14 15 16 17 18 19 20 21 22 23 26 27 28 29
Read/write valid time to E rise tRWV = PWEL - tRWD Read/write hold time Low strobe delay time
Low strobe valid time to E rise tLSV = PWEL - tLSD Low strobe hold time Address access time2
Access time from E rise2 Chip select delay time
Chip select access time2 tACCS = tcyc - tCSD - tDSR Chip select hold time Chip select negated time
NOTES: 1. All timings are calculated for normal port drives. 2. This characteristic is affected by clock stretch. Add N x tcyc where N = 0, 1, 2, or 3, depending on the number of clock stretches.
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1 2 ECLK 22 7 5 ADDR[15:0] 6 3
23 DATA[15:0] READ
11 12
13 DATA[15:0] WRITE
15
14
16 R/W
17
18
19 LSTRB (W/O TAG ENABLED)
20
21
29 26 CS NOTE: Measurement points shown are 20% and 70% of V DD
BUS TIM
27
28
Figure 8 Non-Multiplexed Expansion Bus Timing Diagram
MC68C812A4
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PRELIMINARY
Table 13 SPI Timing VDD = 3.3 Vdc 0.3V, VSS = 0 Vdc, TA = TL to TH , 130 pF load on all SPI pins1
Num Function Operating Frequency Master Slave 1 SCK Period Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock (SCK) High or Low Time Master Slave Sequential Transfer Delay Master Slave Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Slave Access Time Slave MISO Disable Time Data Valid (after SCK Edge) Master Slave Data Hold Time (Outputs) Master Slave Rise Time Input Output Fall Time Input Output Symbol fop Min DC DC 2 2 1/2 1 1/2 1 tcyc - 60 tcyc - 30 1/2 1 30 30 0 30 -- -- -- -- 0 0 -- -- -- -- Max 1/2 1/2 256 -- -- -- -- -- 128 tcyc -- -- -- -- -- -- -- 1 1 50 50 -- -- tcyc - 30 30 tcyc - 30 30 Unit E-clock frequency
tsck
tcyc tcyc tsck tcyc tsck tcyc ns ns tsck tcyc ns ns ns ns tcyc tcyc ns ns ns ns ns ns ns ns
2
tlead
3
tlag
PRELIMINARY
4
twsck
5
ttd
6
tsu
7 8 9 10
thi ta tdis tv
11
tho
12
tri tro tfi tfo
13
NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
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MC68C812A4
SS 1 (OUTPUT) 5 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) 10 MOSI (OUTPUT) MSB OUT 2 MSB IN 2 7 BIT 6 . 10 BIT 6 .
. .1 . .1
1 4 4
12
3
13
LSB IN 11 LSB OUT
1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
SPI MASTER CPHA0
A) SPI Master Timing (CPHA = 0)
SS 1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) 10 MOSI (OUTPUT) PORT DATA MASTER MSB OUT 2 MSB IN 2 7 BIT 6 . 11 BIT 6 .
.. . .1
5 13 12 3
4
12
13
LSB IN
1
MASTER LSB OUT
PORT DATA
1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
SPI MASTER CPHA1
B) SPI Master Timing (CPHA = 1)
Figure 9 SPI Timing Diagram (1 of 2)
MC68C812A4
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PRELIMINARY
SS (INPUT) 5 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT) MSB IN MSB OUT 7 BIT 6 .
. .1
13
12
3
4
4
12
13 9
10 BIT 6 .
. .1
11
11 SEE NOTE
SLAVE LSB OUT
LSB IN
SPI SLAVE CPHA0
PRELIMINARY
NOTE: Not defined but normally MSB of character just received.
A) SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 10 MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) SLAVE 6 MSB IN MSB OUT 7 BIT 6 .
. .1
5 3 13 12
4
12
13
11 BIT 6 .
..
9 1 SLAVE LSB OUT
LSB IN
SPI SLAVE CPHA1
NOTE: Not defined but normally LSB of character just received.
B) SPI Slave Timing (CPHA = 1)
Figure 10 SPI Timing Diagram (2 of 2)
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MC68C812A4

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